Physical-Only Cells (Well Taps, End Caps)

  • These library cells do not have signal connectivity and connect only to the power and ground rails
  • End Caps ensure that gaps do not occur between the Well and Implant Layers and also prevents DRC violations by satisfying Well tie-off requirements for core rows
  • Well Taps help to tie Substrate and N-wells to VDD and VSS levels and thus prevent Latch-up

Special Cells (Spare cells, Decap Cells)

  • Spare Cells for ECO and Decaps for avoiding Instantaneous Voltage Drop (IVD)
  • Place Decaps closer to Power Pads or any larger Drivers
pre placement in physical design

Cell Padding

  • Cell Padding is done to reserve space for avoiding Routing Congestion
  • Cell Padding adds Hard Constraints to Placement
  • The Constraints are honored by Cell, Legalization, CTS, and Timing Optimization

Pre-Placement Optimization

Pre-Placement Optimization Goals

  • Routability
  • Performance (Timing)
  • Power (with Cells)

Optimizations before Placement

  • Delay models must be removed (if any)
  • Zero-RC (0-RC) Optimization
  • Isolation Cell Insertion
  • Multi Corner Multi Mode (MCMM) settings before Std. Cell Placement

Zero-RC Optimization

  • Optimizes the netlist without any delay models, thus provides an optimal starting point for placement
  • Timing during 0-RC Opt and that of during Synthesis has to be matched
  • Else indicate problems in the Technology File, Timing Library, Constraint Files, or overall design
  • Logical restructuring and up/down size are optimizations at the 0-RC stage
Note: Take care of don’t use cells while doing optimization


  • Placement is the process of placing standard cell in the design. the tool determines the location of each standard cell on the die. the tool places these based on the algorithms which it uses internally.

  • Placement does not just place the standard cells available in the synthesized netlist. it also optimizes the design. placement also determines the routability of design.

  • Placement will be driven by different criteria like timing driven, congestion driven and power optimization.
placement in physical design
  • Automated Standard Cell Placement for placing the Standard Cells in Placement Tracks

    Placement Objectives

    • Total wire length
    • Routability
    • Performance
    • Power
    • Heat distribution
  • Timing checks only with slow corners at Placement stage

  • Only Setup Time check, since buffers are getting added during Clock Tree Synthesis

    Goals of Placement:

    • Timing, Power and Area optimizations
    • Minimum congestion
    • Minimal cell density, pin density and congestion hot-spots
    • Minimal timing DRVs

    Inputs of Placement:

    • Technology file (.tf)
    • Netlist
    • SDC
    • Library files (.lib & .lef) & TLU+ file
    • Floorplan & Powerplan DEF file
    placement goals

    Things to be checked before placement

    1. Check for any missing/extra placement & routing blockages.
    2. Don't use cell list and whether it is properly applied in the tool.
    3. Don't touch on cells and nets (make sure that, these are applied).
    4. Better to have limit the local density (otherwise local congestion can create issue in routing/eco stage).
    5. Understand all optimization options and placement switches set in the tool.
    6. There should not be any high WNS timing violations.
    7. Make sure that clock is ideal network.
    8. Take care of integration guidelines of any special IPs (these won't be reported in any of the checks). Have custom scripts to check these guidelines.
    9. Fix all the hard macros and pre-placed cells.
    10. Check the pin access

    • Before the start of placement optimization all wire load model (WLM) are removed.
    • Placement uses RC values from virtual route (VR) to calculate timing.
    • VR is the shortest manhattan distance between two pins.
    • VR RCs is more accurate than WLM RCs.

    Placement Methods

    Timing Driven Placement
    • To Refine placement based on congestion, timing and power
    • To optimize large sets of path delays
    • Net Based
    Congestion Driven Placement
    • To distance standard cell instances from each other such that more routing tracks are created between them

    - Control the delay on signal path by imposing an upper bound delay or weight to net

    placement in physical design

    Global/ Coarse Placement

    • To get the approximate initial location
    • Cells are not legally placed and there can be overlapping

    Detail/ Legal Placement

    • To avoid cell overlapping
    • Cells have legalized locations
    • Legalize placement will place the cells in their legal position with no overlap

    placement steps

    Placement Legalization

    • Placed Macros are legally oriented with Standard Cell Rows

    In-Place Optimizations

    • Scan Chain Reordering: DFT tool flow makes a list of all the scan-able flops in the design, and sorts them based on their hierarchy. In APR tool scan chains are reordered on the basis of placement of flops & Q-SI routing. This is nothing but scan-chain reordering. Scan-chain reordering helps to reduce congestion, total wire-length etc…

    • After Placement, report Congestion, Utilization and Timing
    • Tie off cell instances provide connectivity between the Tiehigh and Tie-low logical inputs pins of the Netlist instances to Power and Ground
    • Tie off cells are placed after the placement of Standard Cells
    • After placement check the Cell Density

    Global Route (GR)

    • Whole region is divided into an array of rectangular sub-regions each of which may accommodate tens of routing tracks in each dimension called Global Cells
    • Global Route is performed to estimate the inter-connect parasitics and Routing Congestion Map

    Placement Opt./ Pre CTS Optimization

    Cell Sizing
    • Sized up/ down to meet optimizing for timing and area
    • Up sizing will give timing advantage and Down sizing will give area advantage
    VT Swapping
    • To optimize for leakage power (HVT, RVT/SVT, LVT)
    • To reduce fanout
    • Long nets are buffered or remove buffers to bring the timing advantage
    • To improve slews, reduce net capacitance and reduce fanout
    Logical Restructuring
    • To optimize timing and area without changing the functionality of the design
    • Breaking complex cells into simpler cells or vice versa
    Pin Swapping

    Optimization techniques
    placement optimization

    Timing Optimization techniques
    placement optimization

    Placement Qualifications

    • Unplaced cells (should be 0)
    • Cells overlap (should be 0)
    • Utilization
    • Minimal timing issue
    • Minimal congestion issue
    • Minimal timing DRVs
    • Total area after optimization

    Placement Output

    • Congestion report
    • Timing report
    • Design with all std cells placed in core area
    • Logs
    • Placement DEF file
    • What is synthesis?
    • Goals of synthesis
    • Synthesis Flow
    • Synthesis (input & output)
    • HDL file gen. & lib setup
    • Reading files
    • Design envi. Constraints
    • Compile
    • Generate Reports
    • Write files
    Go To page
    • Netlist(.v or .vhd)
    • Constraints
    • Liberty Timing File(.lib or .db)
    • Library Exchange Format(LEF)
    • Technology Related files
    • TLU+ File
    • Milkyway Library
    • Power Specification File
    • Optimization Directives
    • Design Exchange Formats
    • Clock Tree Constraints/ Specification
    • IO Information File
    Go To page
    • import design
    • sanity checks
    • partitioning (flat and hierarchy)
    • objectives of floorplan
    • Inputs of floorplan
    • Floorplan flowchart
    • Floorplan Techniques
    • Terminologies and definitions
    • Steps in FloorPlan
    • Utilization
    • IO Placement
    • Macro Placement
    • Macro Placement Tips
    • Blockages (soft,hard,partial)
    • Halo/keepout margin
    • Issues arises due to bad floor-plan)
    • FloorPlan Qualifications
    • FloorPlan Output
    Go To page
    • levels of power distribution
    • Power Management
    • Powerplanning involves
    • Inputs of powerplan
    • Properties of ideal powerplan
    • Power Information
    • PowerPlan calculations
    • Sub-Block configuration
    • fullchip configuration
    • UPF Content
    • Isolation Cell
    • Level Shifters
    • Retention Registers
    • Power Switches
    • Types of Power dissipation
    • IR Drop
    • Electromigration
    Go To page
    • Pre-Placement
    • Pre-Placement Optimization
    • Placement
    • Placement Objectives
    • Goals of Placement
    • Inputs of Placement
    • Checks Before placement
    • Placement Methods(Timing & Congestion)
    • Placement Steps
    • Placement Optimization
    • Placement Qualifications
    • Placement Outputs
    Go To page
    • Pre-CTS Optimization
    • CTS
    • Diff b/w HFNS & CTS
    • Diff b/w Clock & normal buffer
    • CTS inputs
    • CTS Goals
    • Clock latency
    • Clock problems
    • Main concerns for Clock design
    • Clock Skew
    • Clock Jitter
    • CTS Pre requisites
    • CTS Objects
    • CTS Flow
    • Clock Tree Reference
    • Clock Tree Exceptions
    • CTS Algorithm
    • Analyze the Clock tree
    • Post CTS Optimization
    • CTS Outputs
    Go To page
    • Importance of Routing as Technology Shrinks
    • Routing Objectives
    • Routing
    • Routing Inputs
    • Routing Goals
    • Routing constraints
    • Routing Flow
    • Trial/Global Routing
    • Track Assignment
    • Detail/Nano Routing
    • Grid based Routing
    • Routing Preferences
    • Post Routing Optimization
    • Filler Cell Insertion
    • Metal Fill
    • Spare Cells Tie-up/ Tie-down
    Go To page
    • Diff b/w DTA & STA
    • Static Timing Analysis
    • main steps in STA
    • STA(input & output)
    • Timing Report
    • Clocked storage elements
    • Delays
    • Pins related to clock
    • Timing Arc
    • Timing Unate
    • Clock definitions in STA
    • Timing Paths
    • Timing Path Groups
    • Clock Latency
    • Insertion Delay
    • Clock Uncertainty
    • Clock Skew
    • Clock Jitter
    • Glitch
    • Pulse width
    • Duty Cycle
    • Transition/Slew
    • Asynchronous Path
    • Critical Path
    • Shortest Path
    • Clock Gating Path
    • Launch path
    • Arrival Path
    • Required Time
    • Common Path Pessimism(CPP/CRPR)
    • Slack
    • Setup and Hold time
    • Setup & hold time violations
    • Recovery Time
    • Removal Time
    • Recovery & Removal time violations
    • Single Cycle path
    • Multi Cycle Path
    • Half Cycle Path
    • False Path
    • Clock Domain Crossing(CDC)
    • Clock Domain Synchronization Scheme
    • Bottleneck Analysis
    • Multi-VT Cells(HVT LVT SVT)
    • Time Borrowing/Stealing
    • Types of STA (PBA GBA)
    • Diff b/w PBA & GBA
    • Block based STA & Path based STA
    Go To page

    • Congestion Analysis
    • Routing Congestion Analysis
    • Placement Cong. Analysis
    • Routing Congestion causes
    • Congestion Fixes
    • Global & local cong.
    • Congestion Profiles
    Go To page
    • Power Analysis
    • Leakeage Power
    • Switching Power
    • Short Circuit
    • Leakage/static Power
    • Static power Dissipation
    • Types of Static Leakage
    • Static Power Reduction Techniques
    • Dynamic/Switching Power
    • Dynamic Power calculation depends on
    • Types of Dynamic Power
    • Dynamic Power Reduction Techniques
    Go To page
    • IR Drop Analysis
    • Types of IR Drop & their methodologies
    • IR Drop Reasons
    • IR Drop Robustness Checks
    • IR Drop Impacts
    • IR Drop Remedies
    • Ldi/dt Effects
    Go To page

    • Design Parasitics
    • Latch-Up
    • Electrostatic Discharge(ESD)
    • Electromigration
    • Antenna Effect
    • Crosstalk
    • Soft Errors
    • Sef Heating
    Go To page
    • Cells in PD
    • Standard Cells
    • ICG Cells
    • Well Taps
    • End Caps
    • Filler Cells
    • Decap Cells
    • ESD Clamp
    • Spare Cells
    • Tie Cells
    • Delay Cells
    • Metrology Cells
    Go To page
    • IO Pads
    • Types of IO Pads
    Go To page
    • Delay Calculation
    • Delay Models
    • Interconnect Delay Models
    • Cell Delay Models
    Go To page
    • Engineering Change Order
    • Post Synthesis ECO
    • Post Route ECO
    • Post Silicon ECO
    • Metal Layer ECO Example
    Go To page
    • std cell library types
    • Classification wrt density and Vth
    Go To page

    • The Discontinuity
    • Discontinuity: Classification
    • DFM/DFY
    • Yield Classification
    • Why DFM/DFY?
    • DFM/DFY Solution
    • Wire Spreading
    • metal Fill
    • CAA
    • CMP Aware-Design
    • Redundant Via
    • RET
    • Litho Process Check(LPC)
    • Layout Dependent Effects
    • Resolution Enhancement Techniques
    • Types of RET
    • Optical Proximity Correction(OPC)
    • Scattering Bars
    • Multiple Patterning
    • Phase-shift Masking
    • Off-Axis Illumination
    Go To page
    • Corners
    • Need for corner analysis
    • PVT Variations
    • Corner Analysis
    • PVT/RC Corners
    • Temperature Inversion
    • Cross Corner Analysis
    • Modes of Analysis
    • MC/MM Analysis
    • OCV
    • Derating
    • OCV Timing Checks
    • OCV Enhancements
    • AOCV
    • SSTA
    Go To page
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