1. Chip utilization depends on ___.
2. In Soft blockages ____ cells are placed.
3. Why we have to remove scan chains before placement?
4. Delay between shortest path and longest path in the clock is called ____.
5. Cross talk can be avoided by ___.
6. Prerouting means routing of _____.
7. Which of the following metal layer has Maximum resistance?
8. What is the goal of CTS?
9. Usually Hold is fixed ___.
10. To achieve better timing ____ cells are placed in the critical path.
11. Leakage power is inversely proportional to ___.
12. Filler cells are added ___.
13. Search and Repair is used for ___.
14. Maximum current density of a metal is available in ___.
15. More IR drop is due to ___.
16. The minimum height and width a cell can occupy in the design is called as ___.
17. CRPR stands for ___.
18. In OCV timing check, for setup time, ___.
19. Total metal area and(or) perimeter of conducting layer / gate to gate area" is called ___.
20. The Solution for Antenna effect is ___.
21. To avoid cross talk, the shielded net is usually connected to ___.
22. If the data is faster than the clock in Reg to Reg path ___ violation may come.
23. Hold violations are preferred to fix ___.
24. Which of the following is not present in SDC ___?
25. Timing sanity check means (with respect to PD)___.
26. Which of the following is having highest priority at final stage (post routed) of the design ___?
27. Which of the following is best suited for CTS?
28. Max voltage drop will be there at(with out macros) ___.
29. Which of the following is preferred while placing macros ___?
30. Routing congestion can be avoided by ___.
31. Pitch of the wire is ___.
32. In Physical Design following step is not there ___.
33. In technology file if 7 metals are there then which metals you will use for power?
34. If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ?
35. In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the clock period should be ___.
36. Difference between Clock buff/inverters and normal buff/inverters is __.
37. Which configuration is more preferred during floorplaning ?
38. What is the effect of high drive strength buffer when added in long net ?
39. Delay of a cell depends on which factors ?
40. After the final routing the violations in the design ___.
41. Utilisation of the chip after placement optimisation will be ___.
42. What is routing congestion in the design?
43. What are preroutes in your design?
44. Clock tree doesn't contain following cell ___.
45. Power Switch off (PSO) | Power Gating technique in low power is used to reduce
46. Why do we re-order scan chains during placement?
47. Increase in the physical distance of H-tree _________the skew rate.
48. In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?
49. clock buffers are preferred than normal buffers in clock tree building because of