Solutions

Physical Design MCQs


1. Chip utilization depends on ___.



2. In Soft blockages ____ cells are placed.



3. Why we have to remove scan chains before placement?



4. Delay between shortest path and longest path in the clock is called ____.



5. Cross talk can be avoided by ___.



6. Prerouting means routing of _____.



7. Which of the following metal layer has Maximum resistance?



8. What is the goal of CTS?



9. Usually Hold is fixed ___.



10. To achieve better timing ____ cells are placed in the critical path.



11. Leakage power is inversely proportional to ___.



12. Filler cells are added ___.



13. Search and Repair is used for ___.



14. Maximum current density of a metal is available in ___.



15. More IR drop is due to ___.



16. The minimum height and width a cell can occupy in the design is called as ___.



17. CRPR stands for ___.



18. In OCV timing check, for setup time, ___.



19. Total metal area and(or) perimeter of conducting layer / gate to gate area" is called ___.



20. The Solution for Antenna effect is ___.



21. To avoid cross talk, the shielded net is usually connected to ___.



22. If the data is faster than the clock in Reg to Reg path ___ violation may come.



23. Hold violations are preferred to fix ___.



24. Which of the following is not present in SDC ___?



25. Timing sanity check means (with respect to PD)___.



26. Which of the following is having highest priority at final stage (post routed) of the design ___?



27. Which of the following is best suited for CTS?



28. Max voltage drop will be there at(with out macros) ___.



29. Which of the following is preferred while placing macros ___?



30. Routing congestion can be avoided by ___.



31. Pitch of the wire is ___.



32. In Physical Design following step is not there ___.



33. In technology file if 7 metals are there then which metals you will use for power?



34. If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ?



35. In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the clock period should be ___.



36. Difference between Clock buff/inverters and normal buff/inverters is __.



37. Which configuration is more preferred during floorplaning ?



38. What is the effect of high drive strength buffer when added in long net ?



39. Delay of a cell depends on which factors ?



40. After the final routing the violations in the design ___.



41. Utilisation of the chip after placement optimisation will be ___.



42. What is routing congestion in the design?



43. What are preroutes in your design?



44. Clock tree doesn't contain following cell ___.



45. Power Switch off (PSO) | Power Gating technique in low power is used to reduce



46. Why do we re-order scan chains during placement?



47. Increase in the physical distance of H-tree _________the skew rate.



48. In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?



49. clock buffers are preferred than normal buffers in clock tree building because of



  • What is synthesis?
  • Goals of synthesis
  • Synthesis Flow
  • Synthesis (input & output)
  • HDL file gen. & lib setup
  • Reading files
  • Design envi. Constraints
  • Compile
  • Generate Reports
  • Write files
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  • Netlist(.v or .vhd)
  • Constraints
  • Liberty Timing File(.lib or .db)
  • Library Exchange Format(LEF)
  • Technology Related files
  • TLU+ File
  • Milkyway Library
  • Power Specification File
  • Optimization Directives
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  • Clock Tree Constraints/ Specification
  • IO Information File
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  • import design
  • sanity checks
  • partitioning (flat and hierarchy)
  • objectives of floorplan
  • Inputs of floorplan
  • Floorplan flowchart
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  • Utilization
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  • levels of power distribution
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  • Sub-Block configuration
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  • Pre-Placement
  • Pre-Placement Optimization
  • Placement
  • Placement Objectives
  • Goals of Placement
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  • Checks Before placement
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  • Pre-CTS Optimization
  • CTS
  • Diff b/w HFNS & CTS
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  • Analyze the Clock tree
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  • Importance of Routing as Technology Shrinks
  • Routing Objectives
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  • Filler Cell Insertion
  • Metal Fill
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  • Diff b/w DTA & STA
  • Static Timing Analysis
  • main steps in STA
  • STA(input & output)
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  • Clocked storage elements
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  • Transition/Slew
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  • Critical Path
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  • Launch path
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  • Required Time
  • Common Path Pessimism(CPP/CRPR)
  • Slack
  • Setup and Hold time
  • Setup & hold time violations
  • Recovery Time
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  • Recovery & Removal time violations
  • Single Cycle path
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  • False Path
  • Clock Domain Crossing(CDC)
  • Clock Domain Synchronization Scheme
  • Bottleneck Analysis
  • Multi-VT Cells(HVT LVT SVT)
  • Time Borrowing/Stealing
  • Types of STA (PBA GBA)
  • Diff b/w PBA & GBA
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  • Congestion Analysis
  • Routing Congestion Analysis
  • Placement Cong. Analysis
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  • Power Analysis
  • Leakeage Power
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  • Dynamic Power calculation depends on
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  • IR Drop Analysis
  • Types of IR Drop & their methodologies
  • IR Drop Reasons
  • IR Drop Robustness Checks
  • IR Drop Impacts
  • IR Drop Remedies
  • Ldi/dt Effects
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  • Design Parasitics
  • Latch-Up
  • Electrostatic Discharge(ESD)
  • Electromigration
  • Antenna Effect
  • Crosstalk
  • Soft Errors
  • Sef Heating
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  • Cells in PD
  • Standard Cells
  • ICG Cells
  • Well Taps
  • End Caps
  • Filler Cells
  • Decap Cells
  • ESD Clamp
  • Spare Cells
  • Tie Cells
  • Delay Cells
  • Metrology Cells
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  • IO Pads
  • Types of IO Pads
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  • Delay Calculation
  • Delay Models
  • Interconnect Delay Models
  • Cell Delay Models
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  • Engineering Change Order
  • Post Synthesis ECO
  • Post Route ECO
  • Post Silicon ECO
  • Metal Layer ECO Example
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  • std cell library types
  • Classification wrt density and Vth
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  • The Discontinuity
  • Discontinuity: Classification
  • DFM/DFY
  • Yield Classification
  • Why DFM/DFY?
  • DFM/DFY Solution
  • Wire Spreading
  • metal Fill
  • CAA
  • CMP Aware-Design
  • Redundant Via
  • RET
  • Litho Process Check(LPC)
  • Layout Dependent Effects
  • Resolution Enhancement Techniques
  • Types of RET
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  • Multiple Patterning
  • Phase-shift Masking
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  • Corners
  • Need for corner analysis
  • PVT Variations
  • Corner Analysis
  • PVT/RC Corners
  • Temperature Inversion
  • Cross Corner Analysis
  • Modes of Analysis
  • MC/MM Analysis
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  • Derating
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