IR Drop Analysis

Physical Design Analysis

IR Drop Analysis

      IR Drop
  • The voltage that gets to the internal circuitry is less than that applied to the chip, since every metal layer offers resistance to the flow of current
  • When a current, I passes through a conductor with resistor R, it exhibits a voltage drop V which is equal to the resistance times the current,
                                                            Ohm’s law, V=IR
  • IR Drop is defined as the average of the peak currents in the power network multiplied by the effective resistance from the power supply pads to the center of the chip
  • IR Drop is a reduction in voltage that occurs on both Power and Ground networks
  • IR Drop Analysis ensures that Power Delivery Network (PDN) is robust, and that your system will function to specification
  • IR Drop is determined by the current flow and the supply voltage
  • As distance between supply voltage and the component increases the IR Drop also increases
IR Drop Analysis
  • IR Drop Analysis will compute the actual IDD and ISS currents, because these values are time-dependent
  • IR Drop Analysis will compute Global IR drop which is important and more accurate, but cannot be compute separately (parallel) for smaller blocks, which may led to bigger run time
  • Local IR Drop
    • IR Drop become a local phenomenon when a number of gates in close proximity switches at once
    • Local IR Drop can also be caused by a higher resistance to a specific portion of the Grid
  • Global IR Drop
    • IR Drop is a global phenomenon when activity in one region of a chip causes an IR Drop in other regions
  • In a well-meshed power grid with equally distributed currents, the power grid typically has a set of equipotential IR Drop surfaces that form concentric circles cantered in the middle of the chip
  • So the center of the chip usually has the largest IR Drop or the lowest supply voltage
  • Peak IR Drop is much larger than the Average IR Drop
  • Peak IR Drop happens in the worst-case switch patterns of the gates

Types of IR Drop

Static IR Drop
  • Static IR drop is average voltage drop for the design
  • The average current depends totally on the time period
  • Static IR drop was good for signoff analysis in older
    technology nodes where sufficient natural decoupling
    capacitance from the power network and
    non-switching logic were available
  • Localized switching is only considered
  • Only be a few % of the supply voltage
  • Can be reduced by lowering the resistance of Supply
    and Signal Paths
Static IR Drop methodology
  • Extract power grid to obtain R
  • Select stimulus
  • Compute time averaged power consumption for a typical operation to obtain I(current)
  • Compute: V = IR
  • Non time-varying
IR Drop analysis

Dynamic IR Drop
  • When large amounts of circuitry switch simultaneously causing peak current demand
  • Dynamic IR drop is mainly due to Instantaneous Voltage Drop (IVD) and it can be controlled by inserting Decap Cells in the Power network
  • Dynamic IR drop depends on switching activity and switching time of the logic and is less dependent on the a clock period
  • Instantaneous current demand could be highly localized and could be brief within a single clock cycle (a few hundred ps)
  • Vector dependent, so VCD-based analysis is required
Dynamic IR Drop methodology
  • Extract power grid to obtain on-chip R and C
  • Include RLC model of the package and bond wires
  • Select stimulus
  • Compute time varying power for specific operation to obtain I(t)
  • Compute V(t) = I(t)*R + C*dv/dt*R + L*di/dt
 Dynamic IR Drop analysis

IR Drop: Reasons

  • Improper placement of Power/Ground Pads
  • Wrong Block placement
  • Bad global power routing
  • Insufficient Core Ring, Power Strap width
  • Lesser no of Power Straps
  • Missing Vias
  • Insufficient number of Power Pads

IR Drop: Robustness Checks

  • Open circuits
  • Missing or insufficient Vias
  • Current Density violations
  • Insufficient Power Rail design
IR Drop analysis

IR Drop: Impacts

  • IR Drop Analysis confirms that the worst case voltage drop (which is considered for the worst corner for timing) on a chip meets IR Drop targets
  • Impacts in Timing
    • If this Voltage Drop is too severe, the circuit will not get enough voltage, resulting in the malfunction or timing failure
    • If IR Drop increases Clock Skew then it will result in Hold Time Violations
    • If IR Drop increases Signal Skew then it will result in Setup Time Violations
    IR Drop analysis

IR Drop Plot

     Power grid has a set of equipotential surfaces that form concentric circles centered in the middle of a block IR Drop analysis

IR Drop: Remedies

  • Stagger the firing of buffers (bad idea: increases skew)
  • Use different power grid tap points for clock buffers (but it makes routing more complicated for automated tools)
  • Use smaller buffers (but it degrades edge rates/increases delay)
  • Rearrange blocks
  • More VDD pins
  • Connect bottom portion of grid to top portion
  • Distributing supplies symmetrically on the chip
  • Lowering the resistance of Supply and Signal Paths by making supply wires thicker in dimensions than signal wires, R = ρ.L / A
  • Decap insertion can solve Dynamic IR drop, at later stage of the design
  • Amount of decap depends on:
    • Acceptable ripple on VDD-VSS (typically 10% noise budget)
    • Switching activity of logic circuits (usually need 10X switched cap)
    • Current provided by power grid (di/dt)
    • Required frequency response (high frequency operation)

Ldi/dt Effects

  • In addition to IR drop, power system inductance is also an issue
  • Inductance may be due to power pin, power bump or power grid
  • Overall voltage drop is:
                                         Vdrop = IR + Ldi/dt
  • As a solution to this effect, distribute decoupling capacitors (decaps) liberally throughout design
  • What is synthesis?
  • Goals of synthesis
  • Synthesis Flow
  • Synthesis (input & output)
  • HDL file gen. & lib setup
  • Reading files
  • Design envi. Constraints
  • Compile
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  • Write files
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  • Netlist(.v or .vhd)
  • Constraints
  • Liberty Timing File(.lib or .db)
  • Library Exchange Format(LEF)
  • Technology Related files
  • TLU+ File
  • Milkyway Library
  • Power Specification File
  • Optimization Directives
  • Design Exchange Formats
  • Clock Tree Constraints/ Specification
  • IO Information File
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  • import design
  • sanity checks
  • partitioning (flat and hierarchy)
  • objectives of floorplan
  • Inputs of floorplan
  • Floorplan flowchart
  • Floorplan Techniques
  • Terminologies and definitions
  • Steps in FloorPlan
  • Utilization
  • IO Placement
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  • Blockages (soft,hard,partial)
  • Halo/keepout margin
  • Issues arises due to bad floor-plan)
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  • levels of power distribution
  • Power Management
  • Powerplanning involves
  • Inputs of powerplan
  • Properties of ideal powerplan
  • Power Information
  • PowerPlan calculations
  • Sub-Block configuration
  • fullchip configuration
  • UPF Content
  • Isolation Cell
  • Level Shifters
  • Retention Registers
  • Power Switches
  • Types of Power dissipation
  • IR Drop
  • Electromigration
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  • Pre-Placement
  • Pre-Placement Optimization
  • Placement
  • Placement Objectives
  • Goals of Placement
  • Inputs of Placement
  • Checks Before placement
  • Placement Methods(Timing & Congestion)
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  • Pre-CTS Optimization
  • CTS
  • Diff b/w HFNS & CTS
  • Diff b/w Clock & normal buffer
  • CTS inputs
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  • Clock latency
  • Clock problems
  • Main concerns for Clock design
  • Clock Skew
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  • CTS Pre requisites
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  • Clock Tree Reference
  • Clock Tree Exceptions
  • CTS Algorithm
  • Analyze the Clock tree
  • Post CTS Optimization
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  • Importance of Routing as Technology Shrinks
  • Routing Objectives
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  • Post Routing Optimization
  • Filler Cell Insertion
  • Metal Fill
  • Spare Cells Tie-up/ Tie-down
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  • Diff b/w DTA & STA
  • Static Timing Analysis
  • main steps in STA
  • STA(input & output)
  • Timing Report
  • Clocked storage elements
  • Delays
  • Pins related to clock
  • Timing Arc
  • Timing Unate
  • Clock definitions in STA
  • Timing Paths
  • Timing Path Groups
  • Clock Latency
  • Insertion Delay
  • Clock Uncertainty
  • Clock Skew
  • Clock Jitter
  • Glitch
  • Pulse width
  • Duty Cycle
  • Transition/Slew
  • Asynchronous Path
  • Critical Path
  • Shortest Path
  • Clock Gating Path
  • Launch path
  • Arrival Path
  • Required Time
  • Common Path Pessimism(CPP/CRPR)
  • Slack
  • Setup and Hold time
  • Setup & hold time violations
  • Recovery Time
  • Removal Time
  • Recovery & Removal time violations
  • Single Cycle path
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  • Half Cycle Path
  • False Path
  • Clock Domain Crossing(CDC)
  • Clock Domain Synchronization Scheme
  • Bottleneck Analysis
  • Multi-VT Cells(HVT LVT SVT)
  • Time Borrowing/Stealing
  • Types of STA (PBA GBA)
  • Diff b/w PBA & GBA
  • Block based STA & Path based STA
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  • Congestion Analysis
  • Routing Congestion Analysis
  • Placement Cong. Analysis
  • Routing Congestion causes
  • Congestion Fixes
  • Global & local cong.
  • Congestion Profiles
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  • Power Analysis
  • Leakeage Power
  • Switching Power
  • Short Circuit
  • Leakage/static Power
  • Static power Dissipation
  • Types of Static Leakage
  • Static Power Reduction Techniques
  • Dynamic/Switching Power
  • Dynamic Power calculation depends on
  • Types of Dynamic Power
  • Dynamic Power Reduction Techniques
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  • IR Drop Analysis
  • Types of IR Drop & their methodologies
  • IR Drop Reasons
  • IR Drop Robustness Checks
  • IR Drop Impacts
  • IR Drop Remedies
  • Ldi/dt Effects
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  • Design Parasitics
  • Latch-Up
  • Electrostatic Discharge(ESD)
  • Electromigration
  • Antenna Effect
  • Crosstalk
  • Soft Errors
  • Sef Heating
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  • Cells in PD
  • Standard Cells
  • ICG Cells
  • Well Taps
  • End Caps
  • Filler Cells
  • Decap Cells
  • ESD Clamp
  • Spare Cells
  • Tie Cells
  • Delay Cells
  • Metrology Cells
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  • IO Pads
  • Types of IO Pads
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  • Delay Calculation
  • Delay Models
  • Interconnect Delay Models
  • Cell Delay Models
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  • Engineering Change Order
  • Post Synthesis ECO
  • Post Route ECO
  • Post Silicon ECO
  • Metal Layer ECO Example
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  • std cell library types
  • Classification wrt density and Vth
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  • The Discontinuity
  • Discontinuity: Classification
  • Yield Classification
  • Why DFM/DFY?
  • DFM/DFY Solution
  • Wire Spreading
  • metal Fill
  • CAA
  • CMP Aware-Design
  • Redundant Via
  • RET
  • Litho Process Check(LPC)
  • Layout Dependent Effects
  • Resolution Enhancement Techniques
  • Types of RET
  • Optical Proximity Correction(OPC)
  • Scattering Bars
  • Multiple Patterning
  • Phase-shift Masking
  • Off-Axis Illumination
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  • Corners
  • Need for corner analysis
  • PVT Variations
  • Corner Analysis
  • PVT/RC Corners
  • Temperature Inversion
  • Cross Corner Analysis
  • Modes of Analysis
  • MC/MM Analysis
  • OCV
  • Derating
  • OCV Timing Checks
  • OCV Enhancements
  • AOCV
  • SSTA
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