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Logic Synthesis

What is synthesis Goals of synthesis Synthesis Flow Synthesis (input & output) HDL file gen. & lib setup Reading files Constraints Timing paths Constraints Timing Constraints IO Timing Area Combinational Delay Timing Exceptions Design environment Compile Strategies Optimization Optimization Techniques Boundary Optimization Ungrouping Generate Reports Write files

Physical Design Inputs

Netlist(.v or .vhd) Constraints Liberty Timing File(.lib or .db) Library Exchange Format(LEF) Technology Related files TLU+ File Milkyway Library Power Specification File Optimization Directives Design Exchange Formats Clock Tree Constraints/ Specification IO Information File


import design sanity checks partitioning (flat and hierarchy) objectives of floorplan Inputs of floorplan Floorplan flowchart Floorplan Techniques Terminologies and definitions utilization manufacturing grid std cell tile std cell row placement grid routing grid & track flight line, macro Steps in FloorPlan Utilization (Row Configuration, core to pad/IO Spacing) IO Placement Macro Placement Macro Placement Tips Blockages(soft,hard,partial) Halo/keepout margin Issues arises due to bad floor-plan) FloorPlan Qualifications FloorPlan Output


Powerplan levels of power distribution (Rings, Stripes, Rails, Power Vias, Trunks) Power Management(IO and Core) Powerplanning involves Inputs of powerplan Properties of ideal powerplan Power Information PowerPlan calculations Sub-Block configuration fullchip configuration UPF Content Isolation Cell Level Shifters Retention Registers Power Switches Header and Footer switch Power Reduction Techniques Power Gating Clock Gating Voltage & Frequency Scaling Multiple Threshold Voltages Multiple Supply Volages Memory Partitioning Types of Power dissipation Static Power Dissipation Dynamic Power Dissipation IR Drop Electromigration


Pre-Placement Pre-Placement Optimization Placement Placement Objectives Goals of Placement Inputs of Placement Checks Before placement Placement Methods(Timing & Congestion) Placement Steps Placement Optimization Placement Qualifications Placement Outputs

Clock Tree Synthesis

Pre-CTS Optimization CTS Diff b/w HFNS & CTS Diff b/w Clock & normal buffer CTS inputs CTS Goals Clock latency Clock problems Main concerns for Clock design Clock Skew Clock Jitter CTS Pre requisites CTS Objects CTS Flow Clock Tree Reference Clock Tree Exceptions CTS Algorithm Analyze the Clock tree Post CTS Optimization CTS Outputs


Importance of Routing as Technology Shrinks Routing Objectives Routing Routing Inputs Routing Goals Routing constraints Routing Flow Trial/Global Routing Track Assignment Detail/Nano Routing Grid based Routing Routing Preferences Post Routing Optimization Filler Cell Insertion Metal Fill Spare Cells Tie-up/ Tie-down

Static Timing Analysis

Diff b/w DTA & STA Static Timing Analysis main steps in STA STA(input & output) Timing Report Clocked storage elements Delays Pins related to clock Timing Arc Timing Unate Clock definitions in STA Timing Paths Timing Path Groups Clock Latency Insertion Delay Clock Uncertainty Clock Skew Clock Jitter Glitch Pulse width Duty Cycle Transition/Slew Asynchronous Path Critical Path Shortest Path Clock Gating Path Launch path Arrival Path Required Time Common Path Pessimism(CPP/CRPR) Slack Setup and Hold time Setup & hold time violations Recovery Time Recovery & Removal time violations Removal Time Single Cycle path Multi Cycle Path Half Cycle Path False Path Bottleneck Analysis Clock Domain Synchronization Scheme Clock Domain Crossing(CDC) Multi-VT Cells(HVT LVT SVT) Time Borrowing/Stealing Types of STA (PBA GBA) Diff b/w PBA & GBA Block based STA & Path based STA

Physical Design Analysis

Congestion Analysis

Routing Congestion Analysis Placement Cong. Analysis Routing Congestion causes Congestion Fixes Global & local congestion Congestion Profiles

Power Analysis

Power Analysis Leakeage Power Switching Power Short Circuit Leakage/static Power Static power Dissipation Types of Static Leakage Static Power Reduction Techniques Dynamic/Switching Power Dynamic Power calculation Types of Dynamic Power Dynamic Power Reduction Techniques

IR Analysis

IR Drop Analysis Types of IR Drop & their methodologies IR Drop Reasons IR Drop Robustness Checks IR Drop Impacts IR Drop Remedies Ldi/dt Effects

Physical Design Essentials

Issues In Physical Design

Design Parasitics Latch-Up Remedies for Latach-Up Electrostatic Discharge(ESD) Reasons for ESD Human Body Model Machine Model Charged Device Model ESD Protection Electromigration Reason for Electromigration Impact in the design EM Remedies & Precautions Types of EM Checks EM Failure Mechanism EM Rule Types Blacks Equation Antenna Effect Reason for Antenna Effect Impact in the design Remedies for PAE Antenna Ratio Antenna Rules PAE Side Effects Crosstalk Impact of crosstalk Types of crosstalk Remedies to avoid Xtalk Soft Errors Impact in the design Precautions to avoid soft errors Sef Heating

Cells in PD

Standard Cells ICG Cells Well Taps End Caps Filler Cells Decap Cells ESD Clamp Spare Cells Tie Cells Delay Cells Metrology Cells

IO Design

IO Pads Input Output Pads Structure of Pad Implementation Guidelines Pad Limited Design Core Limited Design Types of IO Pads Staggered IO Pads Flip Chip IO Bumps

Delay Models

Delay Calculation Delay Models Interconnect Delay Models Cell Delay Models

Engineering Change Order (ECO)

Engineering Change Order Post Synthesis ECO Post Route ECO Post Silicon ECO Metal Layer ECO Example

Types of Standard Cell Libraries

std cell library types Classification wrt density and Vth

The Discontinuity


std cell library types Classification wrt density and Vth


Corners Need for corner analysis PVT Variations Corner Analysis PVT/RC Corners Temperature Inversion Cross Corner Analysis Modes of Analysis MC/MM Analysis OCV Derating OCV Timing Checks OCV Enhancements AOCV SSTA CRPR/CPPR

Physical Design Question & Answers

500 PD questions answered

Physical Design Verification

Design Rule Check (DRC) Design Rule Examples Base & Metal DRC Layout v/s Schematic (LVS) LVS Flow LVS Input Req. Steps in LVS LVS Checks LVS Errors LVS Check Examples Electrical Rule Check Lithography Process Checking DRC Waivers

STA Numericals

Solved STA Numericals


Physical Design videos

Question & Answer


50+ mcqs

Digital Electronics

Binary Number Systems Basic Gates and Boolean Algebra K-Maps Combinational logic flip-flops Finite State Machines – Synchronous Sequential design Setup time and Hold time Counters and Shift Registers Fault Analysis and Hazards Digital Integrated Circuits Memories, FIFO and Programmable devices

CMOS Fundamentals




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